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| CY8C24123A CY8C24223A, CY8C24423A PSoC(R) Programmable System-on-ChipTM Features Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz 8x8 Multiply, 32-Bit Accumulate Low Power at High Speed 2.4 to 5.25V Operating Voltage Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40C to +85C Advanced Peripherals (PSoC(R) Blocks) Six Rail-to-Rail Analog PSoC Blocks Provide: * Up to 14-Bit ADCs * Up to 9-Bit DACs * Programmable Gain Amplifiers * Programmable Filters and Comparators Four Digital PSoC Blocks Provide: * 8 to 32-Bit Timers, Counters, and PWMs * CRC and PRS Modules * Full-Duplex UART * Multiple SPI Masters or Slaves * Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 MHz Oscillator High accuracy 24 MHz with optional 32 kHz Crystal and PLL Optional External Oscillator, up to 24 MHz Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory 4K Flash Program Storage 50,000 Erase/Write Cycles 256 Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Sink on all GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO Up to Ten Analog Inputs on GPIO Two 30 mA Analog Outputs on GPIO Configurable Interrupt on All GPIO New CY8C24x23A PSoC Device Derived From the CY8C24x23 Device Low Power and Low Voltage (2.4V) Additional System Resources 2 I CTM Slave, Master, and MultiMaster to 400 kHz Watchdog and Sleep Timers User-Configurable Low Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator, and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Logic Block Diagram Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller SROM Global Analog Interconnect Flash 4K Sleep and Watchdog CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Block Array Analog Ref Analog Input Muxing Digital Clocks Multiply Accum. Decimator I2C POR and LVD System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 38-12028 Rev. *J * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised April 14, 2009 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A PSoC Functional Overview The PSoC family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows combining all the device resources into a complete custom system. The PSoC CY8C24x23A family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to 4 digital blocks and 6 analog blocks. Digital System The Digital System consists of 4 digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 1 Port 2 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration 8 8 Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 Row Output Configuration PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watchdog Timers (WDT). Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin's drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can generate a system interrupt on high level, low level, and change from last read. GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations are: PWMs (8 to 32 bit) PWMs with Dead band (8 to 24 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity SPI master and slave I2C slave and multi-master (one is available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This gives a choice of system resources for your application. Family resources are shown in Table 1 on page 4. Document Number: 38-12028 Rev. *J Page 2 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Analog System The Analog System consists of six configurable blocks, each consisting of an opamp circuit that allows the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] Analog-to-digital converters (up to two, with 6 to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (two and four pole band-pass, low-pass, and notch) Amplifiers (up to two, with selectable gain to 48x) Instrumentation amplifiers (one with selectable gain to 93x) Comparators (up to two, with 16 selectable thresholds) DACs (up to two, with 6 to 9-bit resolution) Multiplying DACs (up to two, with 6 to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC Core resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 Analog blocks are arranged in a column of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 2. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource follow: Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks may be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master are supported. Page 3 of 55 Document Number: 38-12028 Rev. *J [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, see the PSoC(R) Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted in this table. Table 1. PSoC Device Characteristics Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks Digital IO SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. Flash Size 32K 16K Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. up to 4 64 up to 2 44 49 1 up to 1 24 16 8 4 4 4 4 4 0 12 12 48 12 12 28 8 28 4 4 2 2 2 0 0 0 4 4 2 2 2 2 2 0 12 12 6 6 6 4[1] 4[1] 3[2] 2K 256 16K Bytes 1K 256 4K Bytes 256 4K Bytes 512 8K Bytes 256 4K Bytes 512 8K Bytes Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CY8C24x23A up to 1 24 CY8C21x34 CY8C21x23 CY8C20x34 up to 1 28 16 1 Cypros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. up to 0 28 Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense. Document Number: 38-12028 Rev. *J Page 4 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Development Tools PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional Integrated Development Environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 38-12028 Rev. *J Page 5 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug property, and other information you may need to successfully implement your design. Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called "user modules". User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver Document Number: 38-12028 Rev. *J Page 6 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 2. Acronyms Used Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR PPOR PSoC(R) PWM SC SLIMO SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-ChipTM pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Units of Measure A unit of measure table is located in the section Electrical Specifications on page 17. Table 8 on page 14 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h' or `b' are decimal. Document Number: 38-12028 Rev. *J Page 7 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Pinouts This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled with a "P") is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinoutt Table 3. Pin Definitions - 8-Pin PDIP and SOIC Pin No. 1 2 3 4 5 6 7 8 Type Pin Description Digital Analog Name I/O I/O P0[5] Analog Column Mux Input and Column Output I/O I/O P0[3] Analog Column Mux Input and Column Output I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK* Power Vss Ground Connection I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA* I/O I P0[2] Analog Column Mux Input I/O I P0[4] Analog Column Mux Input Power Vdd Supply Voltage Figure 3. CY8C24123A 8-Pin PSoC Device A, IO, P0[5] A, IO, P0[3] I2CSCL,XTALin, P1[1] Vss 1 8 2PDIP 7 3SOIC6 4 5 Vdd P0[4], A, I P0[2], A, I P1[0],XTALout,I2CSDA LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *J Page 8 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A 20-Pin Part Pinout Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type Pin Description Digital Analog Name I/O I P0[7] Analog Column Mux Input I/O I/O P0[5] Analog Column Mux Input and Column Output I/O I/O P0[3] Analog Column Mux Input and Column Output I/O I P0[1] Analog Column Mux Input Power SMP Switch Mode Pump (SMP) Connection to External Components required I/O P1[7] I2C Serial Clock (SCL) I/O P1[5] I2C Serial Data (SDA) I/O P1[3] I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK* Power Vss Ground Connection. I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA* I/O P1[2] I/O P1[4] Optional External Clock Input (EXTCLK) I/O P1[6] Input XRES Active High External Reset with Internal Pull Down I/O I P0[0] Analog Column Mux Input I/O I P0[2] Analog Column Mux Input I/O I P0[4] Analog Column Mux Input I/O I P0[6] Analog Column Mux Input Power Vdd Supply Voltage Figure 4. CY8C24223A 20-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] SMP I2CSCL,P1[7] I2C SDA,P1[5] P1[3] I2CSCL, XTALin,P1[1] Vss 1 2 3 4 5 6 7 8 9 10 PDIP SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], A, I P0[4], A, I P0[2], A, I P0[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *J Page 9 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A 28-Pin Part Pinout Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Pin Description Digital Analog Name I/O I P0[7] Analog Column Mux Input I/O I/O P0[5] Analog Column Mux Input and column output I/O I/O P0[3] Analog Column Mux Input and Column Output I/O I P0[1] Analog Column Mux Input I/O P2[7] I/O P2[5] I/O I P2[3] Direct Switched Capacitor Block Input I/O I P2[1] Direct Switched Capacitor Block Input Power SMP Switch Mode Pump (SMP) Connection to External Components required I/O P1[7] I2C Serial Clock (SCL) I/O P1[5] I2C Serial Data (SDA) I/O P1[3] I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK* Power Vss Ground connection. I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA* I/O P1[2] I/O P1[4] Optional External Clock Input (EXTCLK) I/O P1[6] Input XRES Active High External Reset with Internal Pull Down I/O I P2[0] Direct Switched Capacitor Block Input I/O I P2[2] Direct Switched Capacitor Block Input I/O P2[4] External Analog Ground (AGND) I/O P2[6] External Voltage Reference (VRef) I/O I P0[0] Analog Column Mux Input I/O I P0[2] Analog Column Mux Input I/O I P0[4] Analog Column Mux Input I/O I P0[6] Analog Column Mux Input Power Vdd Supply Voltage Figure 5. CY8C24423A 28-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I P0[4], A, I P0[2], A, I P0[0], A, I P2[6],ExternalVRef P2[4],ExternalAGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *J Page 10 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A 32-Pin Part Pinout Table 6. Pin Definitions - 32-Pin QFN** P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I Vdd P0[6], A, I P2[7] P2[5] A, I, P2[3] A, I, P2[1] Vss SMP I2CSCL, P1[7] I2CSDA, P1[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P2[7] P2[5] P2[3] P2[1] Vss SMP P1[7] P1[5] NC P1[3] P1[1] Vss P1[0] P1[2] P1[4] I/O I/O Power I/O I/O I/O Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK* Ground Connection Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA* Optional External Clock Input (EXTCLK) No Connection Figure 9. CY8C24423A 32-Pin Sawn PSoC Device P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I Vdd P0[6], A, I P0[4], A, I NC I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I I I I I I I IO IO I NC P1[6] XRES Active High External Reset with Internal Pull Down P2[0] Direct Switched Capacitor Block Input P2[2] Direct Switched Capacitor Block Input P2[4] External Analog Ground (AGND) P2[6] External Voltage Reference (VRef) P0[0] Analog Column Mux Input P0[2] Analog Column Mux Input NC No Connection P0[4] Analog Column Mux Input P0[6] Analog Column Mux Input Vdd Supply Voltage P0[7] Analog Column Mux Input P0[5] Analog Column Mux Input and Column Output P0[3] Analog Column Mux Input and Column Output P0[1] Analog Column Mux Input P2[7] P2[5] A, I, P2[3] A, I, P2[1] Vss SMP 12 CS CL, P1[7] 12 CS DA, P1[5] 32 31 30 29 28 27 26 25 NC 9 P1[3] 10 I2CSCL,XTALin,P1[1] 11 Vss 12 I2CSDA,XTALout,P1[0] 13 P1[2] 14 EXTCLK,P1[4] 15 NC 16 I/O I/O Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input Ground Connection Switch Mode Pump (SMP) Connection to External Components required I2C Serial Clock (SCL). I2C Serial Data (SDA). No Connection 32 31 30 29 28 27 26 25 P0[4], A, I NC 24 23 22 21 20 19 18 17 P0[2], A, I P0[0], A, I P2[6],External VRef P2[4],External AGND P2[2], A, I P2[0], A, I XRES P1[6] Pin No. Type Digital Analog I/O I/O I/O I I/O I Power Power Pin Name Description Figure 6. CY8C24423A 32-Pin PSoC Device 1 2 3 4 5 6 7 8 QFN (Top View ) 1 2 3 4 5 6 7 8 QFN (Top View) LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. ** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. Document Number: 38-12028 Rev. *J NC P1[3] 12 CS CL, XTALin, P1[1] Vss 12 CS DA, XTALout, P1[0] P1[2] EXTCLK, P1[4] NC 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[2], A, I P0[0], A, I P2[6], ExternalVRef P2[4], ExternalA GND P2[2], A, I P2[0], A, I XRES P1[6] Page 11 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. Pin Definitions - 56-Pin SSOP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Pin Description Digital Analog Name NC No Connection I/O I P0[7] Analog Column Mux Input I/O I P0[5] Analog Column Mux Input and Column Output I/O I P0[3] Analog Column Mux Input and Column Output I/O I P0[1] Analog Column Mux Input I/O P2[7] I/O P2[5] I/O I P2[3] Direct Switched Capacitor Block Input I/O I P2[1] Direct sWitched Capacitor Block Input I/O P4[7] I/O P4[5] I/O I P4[3] I/O I P4[1] OCD OCD OCD Even Data IO. E OCD OCD OCD Odd Data Output O Power SMP Switch Mode Pump (SMP) Connection to required External Components I/O P3[7] I/O P3[5] I/O P3[3] I/O P3[1] I/O P5[3] I/O P5[1] I/O P1[7] I2C Serial Clock (SCL) I/O P1[5] I2C Serial Data (SDA) NC No Connection I/O P1[3] I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK* Power Vdd Supply Voltage NC No Connection NC No Connection I/O P1[0] Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA* I/O P1[2] I/O P1[4] Optional External Clock Input (EXTCLK) Figure 10. CY8C24000A 56-Pin PSoC Device NC AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] NC P1[3] SCLK, I2C SCL, XTALIn, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], AI P0[4], AIO P0[2], AIO P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI P4[6] P4[4] P4[2] P4[0] CCLK HCLK XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALOut, I2C SDA, SDATA NC NC SSOP Not for Production 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Document Number: 38-12028 Rev. *J Page 12 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 7. Pin Definitions - 56-Pin SSOP (continued) Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Type Digital Analog I/O I/O I/O I/O I/O I/O I/O Input OCD OCD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I Pin Name Description I I P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES Active high external reset with internal pull down. HCLK OCD high-speed clock output. CCLK OCD CPU clock output. P4[0] P4[2] P4[4] P4[6] P2[0] Direct switched capacitor block input. P2[2] Direct switched capacitor block input. P2[4] External Analog Ground (AGND). P2[6] External Voltage Reference (VRef). P0[0] Analog column mux input. P0[2] Analog column mux input and column output. P0[4] Analog column mux input and column output. P0[6] Analog column mux input. Vdd Supply voltage. LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details. Document Number: 38-12028 Rev. *J Page 13 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Register Reference This section lists the registers of the CY8C24x23A PSoC device. For detailed register information, refer the PSoC Programmable Sytem-on-Chip Reference Manual. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed. Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table. Table 8. Abbreviations Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Document Number: 38-12028 Rev. *J Page 14 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 9. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 Addr (0,Hex) Access 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE Access ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 RW # RW # RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 # W RW # # W RW # # W RW # # W RW # AMX_IN RW ARF_CR CMP_CR0 ASY_CR CMP_CR1 RW # # RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW RW RW RW CPU_F RL CPU_SCR1 # 3F Blank fields are Reserved and must not be accessed. 7F BF # Access is bit specific. CPU_SCR0 FF # Document Number: 38-12028 Rev. *J Page 15 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 10. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access RW RW RW RW RW RW RW RW Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW RW RW RW DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU RW RW RW RW RW RW RW RW RW RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW RW R AMD_CR1 ALT_CR0 RW RW IMO_TR ILO_TR BDG_TR ECO_TR W W RW W ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW RW RW RW CPU_F RL CPU_SCR1 CPU_SCR0 # # Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12028 Rev. *J Page 16 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications, check if you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Specifications are valid for -40C TA 85C and TJ 100C, except where noted. Refer to Table 31 on page 31 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 11. Voltage versus CPU Frequency Figure 12. IMO Frequency Trim Options SLIMO Mode=1 4.75 Vdd Voltage 3.00 2.40 93 kHz 3 MHz CPUFre que ncy 12 MHz 24 MHz 4.75 Vdd Voltage SLIMO Mode = 0 5.25 5.25 SLIMO Mode=0 The following table lists the units of measure that are used in this section. Table 11. Units of Measure Symbol C dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol W mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 38-12028 Rev. *J lid g Va atin n r pe io O Reg 3.60 3.00 2.40 93 kHz SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 6 MHz IM O Fre que ncy 12 MHz 24 MHz Page 17 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 Units Notes C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25C 25C. Extended duration storage temperatures above 65C degrades reliability. C V V V mA V mA TA Vdd VIO VIOZ IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 - - - - - - - - +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200 Human Body Model ESD. Operating Temperature Table 13. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ - - Max +85 +100 Units Notes C C The temperature rise from ambient to junction is package specific. See Table 50 on page 50. The user must limit the power consumption to comply with this requirement. Document Number: 38-12028 Rev. *J Page 18 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Electrical Characteristics DC Chip-Level Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 14. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 2.4 - Typ - 5 Max 5.25 8 Units Notes V See DC POR and LVD specifications, Table 29 on page 29. mA Conditions are Vdd = 5.0V, TA = 25C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. mA Conditions are Vdd = 3.3V, TA= 25 C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. SLIMO mode = 0. IMO = 24 MHz. mA Conditions are Vdd = 2.7V, TA = 25C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz, analog power = off. SLIMO mode = 1. IMO = 6 MHz. A Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40C TA 55C, analog power = off. A Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55C < TA 85C, analog power = off. A Conditions are with properly loaded, 1 W max, 32.768 kHz crystal. Vdd = 3.3V, -40C TA 55C, analog power = off. A Conditions are with properly loaded, 1W max, 32.768 kHz crystal. Vdd = 3.3 V, 55C < TA 85C, analog power = off. V Trimmed for appropriate Vdd. Vdd > 3.0V V Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V IDD3 Supply Current - 3.3 6.0 IDD27 Supply Current - 2 4 ISB ISBH ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[3] - 3 6.5 - 4 25 - 4 7.5 ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[3] VREF VREF27 Reference Voltage (Bandgap) Reference Voltage (Bandgap) - 5 26 1.28 1.16 1.30 1.30 1.33 1.33 Note 3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled. Document Number: 38-12028 Rev. *J Page 19 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 15. 5V and 3.3V DC GPIO Specifications Symbol Description RPU Pull up Resistor Pull down Resistor RPD High Output Level VOH Min 4 4 Vdd - 1.0 Typ 5.6 5.6 - Max 8 8 - Units Notes k k V IOH = 10 mA, Vdd = 4.75 to 5.25V (maximum 40 mA on even port pins (for example, P0[2], P1[4]), maximum 40 mA on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. V IOL = 25 mA, Vdd = 4.75 to 5.25V (maximum 100 mA on even port pins (for example, P0[2], P1[4]), maximum 100 mA on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. V Vdd = 3.0 to 5.25 V Vdd = 3.0 to 5.25 mV nA Gross tested to 1 A pF Package and pin dependent. Temp = 25C pF Package and pin dependent. Temp = 25C VOL Low Output Level - - 0.75 VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.1 - - - - - - 60 1 3.5 3.5 0.8 - - 10 10 Table 16. 2.7V DC GPIO Specifications Symbol Description Pull up Resistor RPU Pull down Resistor RPD High Output Level VOH VOL VIL VIH VH IIL CIN COUT Low Output Level Min 4 4 Vdd - 0.4 Typ 5.6 5.6 - Max 8 8 - Units Notes k k V IOH = 2 mA (6.25 Typ), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA Typ combined IOH budget). V IOL = 11.25 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). V Vdd = 2.4 to 3.0 V Vdd = 2.4 to 3.0 mV nA Gross tested to 1 A pF Package and pin dependent. Temp = 25oC pF Package and pin dependent. Temp = 25oC - - 0.75 Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output - 2.0 - - - - - - 90 1 3.5 3.5 0.75 - - - 10 10 Document Number: 38-12028 Rev. *J Page 20 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25C and are for design guidance only. Table 17. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min - - - - - - 0.0 0.5 Typ 1.6 1.3 1.2 7.0 20 4.5 - - Max 10 8 7.5 35.0 - 9.5 Units mV mV mV Notes TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) Open Loop Gain Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = High Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio GOLOA 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 - - - - V/C pA Gross tested to 1 A pF Package and pin dependent. Temp = 25C Vdd V The common-mode input voltage Vdd - 0.5 range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. - dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. - - - 0.2 0.2 0.5 V V V V V V A A A A A A dB - - - - - - - - - - - - 64 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd Document Number: 38-12028 Rev. *J Page 21 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 18. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min - - - - - 0.2 Typ 1.65 1.32 7.0 20 4.5 - Max 10 8 35.0 - 9.5 Vdd - 0.2 Units mV mV V/C pA pF V Gross tested to 1 A Package and pin dependent. Temp = 25C The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Notes TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA GOLOA Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - dB VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio - - - - - - - - - 0.2 0.2 0.2 V V V V V V - - - - - - 64 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd PSRROA Document Number: 38-12028 Rev. *J Page 22 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 19. 2.7V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min - - - - - 0.2 Typ 1.65 1.32 7.0 20 4.5 - Max 10 8 35.0 - 9.5 Vdd - 0.2 Units mV mV V/C pA pF V Gross tested to 1 A Package and pin dependent. Temp = 25C The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Notes TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA GOLOA Open Loop Gain Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 - - - - - dB VOHIGHOA High Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High is 5V only VOLOWOA Low Output Voltage Swing (internal signals) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = Low Power = High, Opamp Bias = Low ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio - - - - - - - - - 0.2 0.2 0.2 V V V V V V - - - - - - 64 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 - A A A A A A dB Vss VIN (Vdd - 2.25) or (Vdd - 1.25V) VIN Vdd PSRROA DC Low Power Comparator Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 20. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 - - Typ - 10 2.5 Max Vdd - 1 40 30 Units V A mV Document Number: 38-12028 Rev. *J Page 23 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 21. 5V DC Analog Output Buffer Specifications Description Min Input Offset Voltage (Absolute Value) - Average Input Offset Voltage Drift - Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low - Power = High - VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) 0.5 x Vdd + 1.1 Power = Low 0.5 x Vdd + 1.1 Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low - Power = High - ISOB Supply Current Including Bias Cell (No Load) - Power = Low - Power = High PSRROB Supply Voltage Rejection Ratio 52 Table 22. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Min Input Offset Voltage (Absolute Value) - Average Input Offset Voltage Drift - Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low - Power = High - VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low 0.5 x Vdd + 1.0 Power = High 0.5 x Vdd + 1.0 VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low - Power = High - ISOB Supply Current Including Bias Cell (No Load) Power = Low - Power = High PSRROB Supply Voltage Rejection Ratio 52 Typ 3 +6 1 1 Max 12 - Vdd - 1.0 - - Units mV V/C V W W Notes Symbol VOSOB TCVOSOB VCMOB ROUTOB Typ 3 +6 - 1 1 - - Max 12 - Vdd - 1.0 - - - - Units mV V/C V W W V V Notes - - 1.1 2.6 64 .5 x Vdd - 1.3 0.5 x Vdd - 1.3 5.1 8.8 - V V mA mA dB VOUT > (Vdd - 1.25). - - - - V V - - 0.8 2.0 64 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 2.0 4.3 - V V mA mA dB VOUT > (Vdd - 1.25) Document Number: 38-12028 Rev. *J Page 24 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 23. 2.7V DC Analog Output Buffer Specifications Symbol VOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Common-Mode Input Voltage Range Output Resistance Power = Low Power = High Min - - 0.5 - - Typ 3 +6 1 1 Max 12 - Vdd - 1.0 - - Units mV V/C V W W V V Notes TCVOSOB Average Input Offset Voltage Drift VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low 0.5 x Vdd + 0.2 Power = High 0.5 x Vdd + 0.2 VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High ISOB PSRROB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio - - - - - - - - 0.8 2.0 64 0.5 x Vdd - 0.7 0.5 x Vdd - 0.7 2.0 4.3 - V V - 52 mA mA dB VOUT > (Vdd - 1.25). DC Switch Mode Pump Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 24. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V VPUMP 3V VPUMP 2V IPUMP Description 5V Output Voltage from Pump Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configuration listed in footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration listed in footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration listed in footnote.a Average, neglecting ripple. SMP trip voltage is set to 2.55V. Configuration listed in footnote.a SMP trip voltage is set to 5.0V. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 2.55V. Configuration listed in footnote.a SMP trip voltage is set to 5.0V. Configuration listed in footnote.a SMP trip voltage is set to 3.25V. Configuration listed in footnote.a SMP trip voltage is set to 2.55V. Configuration listed in footnote.a 0C TA 100. 1.25V at TA = -40C 3.3V Output Voltage from Pump 3.00 3.25 3.60 V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Available Output Current VBAT = 1.8V, VPUMP = 5.0V VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump 5 8 8 1.8 1.0 1.0 1.2 - - - - - - - - - - 5.0 3.3 3.0 - mA mA mA V V V V VBAT5V VBAT3V VBAT2V VBATSTART Document Number: 38-12028 Rev. *J Page 25 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 24. DC Switch Mode Pump (SMP) Specifications (continued) Symbol VPUMP_Line Description Line Regulation (over VBAT range) Min - Typ 5 Max - Units %VO Notes Configuration listed in footnote.[4] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 29 on page 29. Configuration listed in footnote.[4] VO is the "Vdd Value for PUMP Trip" specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 29 on page 29. Configuration listed in footnote.[4] Load is 5 mA. Configuration listed in footnote.[4] Load is 5 mA. SMP trip voltage is set to 3.25V. VPUMP_Load Load Regulation - 5 - %VO VPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) E3 E2 FPUMP DCPUMP Efficiency - 35 100 50 - - mVpp % Efficiency Switching Frequency Switching Duty Cycle - - 1.3 50 - - MHz % Figure 13. Basic Switch Mode Pump Circuit D1 Vdd L1 V BAT V PUMP + SMP Battery PSoC Vss C1 Note 4. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 13. Document Number: 38-12028 Rev. *J Page 26 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Analog Reference Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 25. 5V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Block to Block Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2 P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.04 2 x BG - 0.048 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.022 -0.034 Typ 1.30 Vdd/2 - 0.01 2 x BG - 0.030 P2[4] BG + 0.008 1.6 x BG - 0.010 0.000 Max 1.33 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.016 1.6 x BG + 0.018 0.034 Units V V V V V V V V V V V V V V V V V V Vdd/2 + BG - 0.10 Vdd/2 + BG Vdd/2 + BG + 0.10 3 x BG - 0.06 3 x BG 3 x BG + 0.06 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077 P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100 3.2 x BG - 0.112 3.2 x BG 3.2 x BG + 0.076 Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04 BG - 0.06 BG BG + 0.06 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 Table 26. 3.3V DC Analog Reference Specifications Symbol BG - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Column to Column Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) Min 1.28 Vdd/2 - 0.03 P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.027 -0.034 Typ 1.30 Vdd/2 - 0.01 Not Allowed P2[4] + 0.001 BG + 0.005 1.6 x BG - 0.010 0.000 Not Allowed Not Allowed Not Allowed Not Allowed Max 1.33 Vdd/2 + 0.005 P2[4] + 0.009 BG + 0.015 1.6 x BG + 0.018 0.034 Units V V V V V mV Document Number: 38-12028 Rev. *J Page 27 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 26. 3.3V DC Analog Reference Specifications (continued) Symbol Description Min Typ Max Units - RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057 V P2[6] = 0.5V) - RefHi = 3.2 x BandGap Not Allowed - RefLo = Vdd/2 - BandGap Not Allowed - RefLo = BandGap Not Allowed - RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed - RefLo = P2[4] - BandGap (P2[4] = Vdd/2) Not Allowed - RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092 V P2[6] = 0.5V) Table 27. 2.7V DC Analog Reference Specifications Symbol BG - - - - - - - - - - - - - - - - - Description Bandgap Voltage Reference AGND = Vdd/2 AGND = 2 x BandGap AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap AGND = 1.6 x BandGap AGND Column to Column Variation (AGND = Vdd/2) RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] - BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.16 Vdd/2 - 0.03 P2[4] - 0.01 BG - 0.01 -0.034 Typ 1.30 Vdd/2 - 0.01 Not Allowed P2[4] BG Not Allowed 0.000 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.01 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4]- P2[6] + 0.01 Max 1.33 Vdd/2 + 0.01 P2[4] + 0.01 BG + 0.015 0.034 Units V V V V mV P2[4] + P2[6] - 0.08 P2[4] + P2[6] + 0.06 V P2[4] - P2[6] - 0.05 P2[4] - P2[6] + 0.09 V Document Number: 38-12028 Rev. *J Page 28 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Analog PSoC Block Specifications Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 28. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) Min - - Typ 12.2 80 Max - - Units k fF Notes DC POR, SMP, and LVD Specifications Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for more information on the VLT_CR register. Table 29. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.36 2.82 4.55 2.450 2.920 3.02 3.13 4.48 4.64 4.73 4.81 2.550 3.02 3.10 3.250 4.64 4.73 4.82 5.00 Max 2.40 2.95 4.70 2.51[5] 2.99[6] 3.09 3.20 4.55 4.75 4.83 4.95 2.62[7] 3.09 3.16 3.32[8] 4.74 4.83 4.92 5.12 Units V V V V0 V0 V0 V0 V0 V V V V V0 V0 V0 V0 V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. - 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.500 2.96 3.03 3.18 4.54 4.62 4.71 4.89 Notes 5. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply. 6. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply. 7. Always greater than 50 mV above VLVD0. 8. Always greater than 50 mV above VLVD3. Document Number: 38-12028 Rev. *J Page 29 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A DC Programming Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 30. DC Programming Specifications Symbol Description VddIWRIT Supply Voltage for Flash Write Operations E Min 2.70 - - 2.1 - - - Vdd - 1.0 50,000 1,800,000 10 Typ - 5 - - - - - - - - - Max - 25 0.8 - 0.2 1.5 Vss + 0.75 Vdd - - - Units V mA V V mA mA V V - - Years Notes Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENP Flash Endurance (per block) FlashENT Flash Endurance (total)[9] FlashDR Flash Data Retention B IDDP VILP VIHP IILP Driving internal pull down resistor. Driving internal pull down resistor. Erase/write cycles per block Erase/write cycles Note 9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 38-12028 Rev. *J Page 30 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 31. 5V and 3.3V AC Chip-Level Specifications Symbol FIMO24 FIMO6 FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Description Internal Main Oscillator Frequency for 24 MHz Internal Main Oscillator Frequency for 6 MHz CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency Min 23.4 Typ 24 Max Units Notes [10,11,12] MHz Trimmed for 5V or 3.3V operation 24.6 using factory trim values. See Figure 12 on page 17. SLIMO mode = 0. 6.35[10,11,12] MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 12 on page 17. SLIMO mode = 1. 24.6[10,11] MHz 12.3[11,12] MHz [10,11,13] MHz Refer to the AC Digital Block 49.2 Specifications. 24.6[11,13] MHz 64 kHz - - 600 10 50 2620 3800 Accuracy is capacitor and crystal dependent. 50% duty cycle. MHz Is a multiple (x732) of crystal frequency. ps ms ms ms ms kHz 5.75 6 0.93 0.93 0 0 15 - - - 0.5 0.5 - - 24 12 48 24 32 32.768 23.986 - - - 1700 2800 Jitter24M2 24 MHz Period Jitter (PLL) TPLLSLEW PLL Lock Time TPLLSLEWSL PLL Lock Time for Low Gain Setting OW TOS TOSACC External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V Vdd 5.5V, -40 oC TA 85 oC. 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Peak-to-Peak Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean Squared FMAX Maximum frequency of signal on row input or row output. TRAMP Supply Ramp Time Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1P - 10 40 - 46.8 - - - 0 100 - 50 50 48.0 300 - - - - 60 - 49.2[10,12] ns s % kHz MHz Trimmed. Using factory trim values. ps ps MHz s 600 12.3 - Notes 10. 4.75V < Vdd < 5.25V. 11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 12. 3.0V < Vdd < 3.6V. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on trimming for operation at 3.3V. 13. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 38-12028 Rev. *J Page 31 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 32. 2.7V AC Chip-Level Specifications Symbol FIMO12 FIMO6 FCPU1 FBLK27 F32K1 Jitter32k TXRST DC12M Jitter12M1P Jitter12M1R FMAX TRAMP Description Internal Main Oscillator Frequency for 12 MHz Internal Main Oscillator Frequency for 6 MHz CPU Frequency (2.7V Nominal)0 Digital PSoC Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency 32 kHz Period Jitter External Reset Pulse Width 12 MHz Duty Cycle 12 MHz Period Jitter (IMO) Peak-to-Peak 12 MHz Period Jitter (IMO) Root Mean Squared Maximum frequency of signal on row input or row output. Supply Ramp Time Min 11.5 Typ 12 Max Units Notes 12.7[14,15,16] MHz Trimmed for 2.7V operation using factory trim values. See Figure 12 on page 17. SLIMO mode = 1. 6.35[14,15,16] MHz Trimmed for 2.7V operation using factory trim values. See Figure 12 on page 17. SLIMO mode = 1. [14,15] 0 3.15 MHz 12.7[14,15,16] MHz0 Refer to the AC Digital Block Specifications. 96 kHz ns s % ps ps MHz s 5.75 0.930 0 8 - 10 40 - - - 0 6 30 12 32 150 - 50 340 - - - - 60 600 12.7 - Notes 14. 2.4V < Vdd < 3.0V. 15. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 16. See Application Note AN2012 "Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation" for information on maximum frequency for User Modules. Document Number: 38-12028 Rev. *J Page 32 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 14. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 15. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 16. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 17. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 Document Number: 38-12028 Rev. *J Page 33 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A AC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 33. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ - - - 27 22 Max 12 18 18 - - Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Table 34. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 6 6 18 18 Typ - - - 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Figure 19. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document Number: 38-12028 Rev. *J Page 34 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A AC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V. Table 35. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units s s s s s s V/s V/s V/s V/s V/s V/s MHz MHz MHz nV/rt-Hz - - - - - - 3.9 0.72 0.62 TSOA - - - 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 - - - - - - - - - - - - - 100 5.9 0.92 0.72 - - - - - - - - - - SRROA SRFOA BWOA ENOA Table 36. 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units s s s s V/s V/s V/s V/s MHz MHz nV/rt-Hz - - - - 3.92 0.72 TSOA - - 0.31 2.7 0.24 1.8 0.67 2.8 - - - - - - - - - 100 5.41 0.72 - - - - - - - SRROA SRFOA BWOA ENOA Document Number: 38-12028 Rev. *J Page 35 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 37. 2.7V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time from 20% of V to 0.1% of V (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units - - - - 3.92 0.72 s s TSOA - - 0.31 2.7 0.24 1.8 0.67 2.8 - - - - - - - - - 100 5.41 0.72 - - - - - - - s s V/s V/s V/s V/s MHz MHz nV/rt-Hz SRROA SRFOA BWOA ENOA Document Number: 38-12028 Rev. *J Page 36 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 20. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 21. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 38-12028 Rev. *J Page 37 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A AC Low Power Comparator Specifications Table 38 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V at 25C and are for design guidance only. Table 38. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min - Typ - Max 50 Units s Notes 50 mV overdrive comparator reference set within VREFLPC AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 39. 5V and 3.3V AC Digital Block Specifications Function Timer Description Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd 4.75V, 2 Stop Bits 20 50[17] 50[17] - - - - - 50[17] - - - - - - - - - - - - - - - - - - - - 49.2 49.2 24.6 8.2 4.1 - 24.6 49.2 24.6 49.2 ns ns ns MHz MHz MHz MHz ns ns MHz MHz MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Min 50[17] - - 50[17] - - Typ - - - - - - Max - 49.2 24.6 - 49.2 24.6 Units ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V 4.75V < Vdd < 5.25V Notes Note 17. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12028 Rev. *J Page 38 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 40. 2.7V AC Digital Block Specifications Function Description Min Typ Max 12.7 100[18] - 100[18] - - 20 100[18] 100[18] - - -0 - -0 - - - -0 -0 - - -0 12.7 -0 12.7 12.7 - -0 -0 12.7 12.7 Units MHz ns MHz ns MHz MHz ns ns ns MHz MHz Notes 2.4V < Vdd < 3.0V All Maximum Block Clocking Frequency Functions Timer Counter Capture Pulse Width Maximum Frequency, With or Without Capture Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode0 Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency - - 12.7 MHz - - 100[18] - - - - -0 - - 6.35 4.23 -0 12.7 12.7 MHz ns ns MHz MHz Maximum data rate at 3.17 MHz due to 2 x over clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum data rate at 1.59 MHz due to 8 x over clocking. Note 18. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 38-12028 Rev. *J Page 39 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A AC Analog Output Buffer Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 41. 5V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.65 0.65 0.65 0.65 0.8 0.8 300 300 Typ - - - - - - - - - - - - Max 2.5 2.5 2.2 2.2 - - - - - - - - Units s s s s V/s V/s V/s V/s MHz MHz kHz kHz Table 42. 3.3V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.5 0.5 0.5 0.5 0.7 0.7 200 200 Typ - - - - - - - - - - - - Max 3.8 3.8 2.6 2.6 - - - - - - - - Units s s s s V/s V/s V/s V/s MHz MHz kHz kHz Document Number: 38-12028 Rev. *J Page 40 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 43. 2.7V AC Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High Min - - - - 0.4 0.4 0.4 0.4 0.6 0.6 180 180 Typ - - - - - - - - - - - - Max 4 4 3 3 - - - - - - - - Units s s s s V/s V/s V/s V/s MHz MHz kHz kHz AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 44. 5V AC External Clock Specifications Symbol FOSCEXT Frequency - - - High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 Typ - - - - Max 24.6 5300 - - Units MHz ns ns s Table 45. 3.3V AC External Clock Specifications Symbol Description 1[19] Min 0.093 0.186 41.7 41.7 150 Typ - - - - - Max 12.3 24.6 5300 - - Units MHz MHz ns ns s FOSCEXT Frequency with CPU Clock divide by - - - FOSCEXT Frequency with CPU Clock divide by 2 or greater[20] High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Notes 19. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 20. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met Document Number: 38-12028 Rev. *J Page 41 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 46. 2.7V AC External Clock Specifications Symbol FOSCEXT FOSCEXT - - - Description Frequency with CPU Clock divide by 1[21] Frequency with CPU Clock divide by 2 or greater[22] High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Min 0.093 0.186 41.7 41.7 150 Typ - - - - - Max 12.3 12.3 5300 - - Units MHz MHz ns ns s AC Programming Specifications Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 47. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Setup Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 - - - - - Typ - - - - - 20 20 - - - Max 20 20 - - 8 - - 45 50 70 Units Notes ns ns ns ns MHz ms ms ns Vdd > 3.6 ns 3.0 Vdd 3.6 ns 2.4 Vdd 3.0 AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 Max 100 - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[23] Max 400 - - - - - - Units kHz s s s s s ns Notes 21. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 22. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. 23. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT S 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 38-12028 Rev. *J Page 42 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Table 48. AC Characteristics of the I2C SDA and SCL Pins for Vdd > 3.0V (continued) Symbol TSUSTOI2C TBUFI2C TSPI2C Description Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Standard Mode Min 4.0 4.7 - Max - - - Fast Mode Min 0.6 1.3 0 Max - - 50 Units s s ns Table 49. AC Characteristics of the I2C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 - Max 100 - - - - - - - - - Fast Mode Min - - - - - - - - - - Max - - - - - - - - - - Units kHz s s s s s ns s s ns Figure 22. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Document Number: 38-12028 Rev. *J Page 43 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Packaging Information This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 23. 8-Pin (300-Mil) PDIP 0.380 0.390 4 1 PIN 1 ID DIMENSIONS IN INCHES MIN. 0.240 0.260 MAX. 5 8 0.100 BSC. SEATING PLANE 0.300 0.325 0.180 MAX. 0.115 0.145 0.125 0.140 0.015 MIN. 0.008 0.015 0-10 0.055 0.070 0.014 0.022 0.430 MAX. 51-85075 *A Document Number: 38-12028 Rev. *J Page 44 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 24. 8-Pin (150-Mil) SOIC PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] X 45 0.016[0.406] 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.050[1.270] BSC 51-85066 *C Figure 25. 20-Pin (300-Mil) Molded DIP 20-Lead (300-Mil) Molded DIP P5 51-8501151-85011-A *A Document Number: 38-12028 Rev. *J Page 45 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 26. 20-Pin (210-Mil) SSOP 51-85077 *C Figure 27. 20-Pin (300-Mil) Molded SOIC 51-85024 *C Document Number: 38-12028 Rev. *J Page 46 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 28. 28-Pin (300-Mil) Molded DIP 51-85014 *D Figure 29. 28-Pin (210-Mil) SSOP 51-85079 *C Document Number: 38-12028 Rev. *J Page 47 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 30. 28-Pin (300-Mil) Molded SOIC 51-85026 *D Figure 31. 32-Pin (5x5 mm) QFN X = 138 MIL Y = 138 MIL 51-85188 *C Document Number: 38-12028 Rev. *J Page 48 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Figure 32. 32-Pin Sawn QFN Package SO LDERABLE EXPOSED PAD NOTES: 1. H A T C H A R E A IS S O LD E R A B LE E X P O S E D P A D 2 . B A S E D O N R E F J E D E C # M O -220 3 . P A C K A G E W E IG H T: 0.058g 4 . D IM E N S IO N S A R E IN M ILL IM E T E R S 001-30999 *A CYPRESS C O M P A N Y C O N F ID E N T IA L T IT LE 3 2L Q F N 5 X 5 X 0 9 0 M M P A C K A G E O U T L IN E 3 5 X 3 5 E P A D (S A W N T Y P E ) Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Figure 33. 56-Pin (300-Mil) SSOP 32 51-85062 *C Document Number: 38-12028 Rev. *J Page 49 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Thermal Impedances Table 50. Thermal Impedances per Package Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 QFN Capacitance on Crystal Pins Table 51. Typical Package Capacitance on Crystal Pins Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 QFN Typical JA [24] 123C/W 185C/W 109C/W 117 C/W 81C/W 69 C/W 101C/W 74 C/W 22C/W Package Capacitance 2.8 pF 2.0 pF 3.0 pF 2.6 pF 2.5 pF 3.5 pF 2.8 pF 2.7 pF 2.0 pF Solder Reflow Peak Temperature The following table lists the minimum solder reflow peak temperatures to achieve good solderability. Table 52. Solder Reflow Peak Temperature Package 8 PDIP 8 SOIC 20 PDIP 20 SSOP 20 SOIC 28 PDIP 28 SSOP 28 SOIC 32 QFN Minimum Peak Temperature[25] 240C 240C 240C 240C 220C 240C 240C 220C 240C Maximum Peak Temperature 260C 260C 260C 260C 260C 260C 260C 260C 260C Notes 24. TJ = TA + POWER x JA 25. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 38-12028 Rev. *J Page 50 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C24x23A family. iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples Software PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Used by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. C Compilers PSoC Designer comes with a free HI-TECH C Lite C compiler. The HI-TECH C Lite compiler is free, supports all PSoC devices, integrates fully with PSoC Designer and PSoC Express, and runs on Windows versions up to 32-bit Vista. Compilers with additional features are available at additional cost from their manufactures. CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes: PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples HI-TECH C PRO for the PSoC is available from http://www.htsoft.com. ImageCraft Cypress Edition Compiler is available from http://www.imagecraft.com. Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: Development Kits All development kits can be purchased from the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter Document Number: 38-12028 Rev. *J Page 51 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Accessories (Emulation and Programming) Table 53. Emulation and Programming Accessories Part # All non-QFN Pin Package All non QFN Flex-Pod Kit[26] CY3250-24X23A Foot Kit[27] CY3250-8DIP-FK, CY3250-8SOIC-FK, CY3250-20DIP-FK, CY3250-20SOIC-FK, CY3250-20SSOP-FK, CY3250-28DIP-FK, CY3250-28SOIC-FK, CY3250-28SSOP-FK CY3250-32QFN-FK Adapter[28] Adapters can be found at http://www.emulation.com. CY8C24423A-24LFXI 32 QFN CY3250-24X23AQFN Third Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see application note AN2323 "Debugging - Build a PSoC Emulator into Your Board". Notes 26. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 27. Foot kit includes surface mount feet that can be soldered to the target PCB. 28. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 38-12028 Rev. *J Page 52 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Ordering Information The following table lists the CY8C24x23A PSoC device's key package features and ordering codes. Table 54. CY8C24x23A PSoC Device Key Features and Ordering Information Analog Outputs 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Analog Blocks Digital IO Pins Analog Inputs Digital Blocks Switch Mode Pump Temperature Range XRES Pin No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes [+] Feedback Ordering Code Package 8 Pin (300 Mil) DIP 8 Pin (150 Mil) SOIC 8 Pin (150 Mil) SOIC (Tape and Reel) 20 Pin (300 Mil) DIP 20 Pin (210 Mil) SSOP 20 Pin (210 Mil) SSOP (Tape and Reel) 20 Pin (300 Mil) SOIC 20 Pin (300 Mil) SOIC (Tape and Reel) 28 Pin (300 Mil) DIP 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 28 Pin (300 Mil) SOIC 28 Pin (300 Mil) SOIC (Tape and Reel) 32 Pin (5x5 mm) QFN 32 Pin (5x5 mm 1.00 MAX) SAWN QFN 32 Pin (5x5 mm 1.00 MAX) SAWN QFN (Tape and Reel) 56 Pin OCD SSOP CY8C24123A-24PXI CY8C24123A-24SXI CY8C24123A-24SXIT CY8C24223A-24PXI CY8C24223A-24PVXI CY8C24223A-24PVXIT CY8C24223A-24SXI CY8C24223A-24SXIT CY8C24423A-24PXI CY8C24423A-24PVXI CY8C24423A-24PVXIT CY8C24423A-24SXI CY8C24423A-24SXIT CY8C24423A-24LFXI CY8C24423A-24LTXI CY8C24423A-24LTXIT 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K 4K Flash (Bytes) 256 256 256 256 256 256 256 256 256 256 256 256 256 256 SRAM (Bytes) No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 -40C to +85C 4 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 16 16 16 16 24 24 24 24 24 24 24 24 24 4 4 4 8 8 8 8 8 10 10 10 10 10 10 10 10 10 256 Yes 256 Yes 256 Yes CY8C24000A-24PVXI[29] 4K Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Ordering Code Definitions CY 8 C 24 xxx-SPxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Note 29. This part may be used for in-circuit debugging. It is NOT available for production Document Number: 38-12028 Rev. *J Page 53 of 55 CY8C24123A CY8C24223A, CY8C24423A Document History Page Document Title: CY8C24123A, CY8C24223A, CY8C24423A PSoC(R) Programmable System-on-ChipTM Document Number: 38-12028 Rev. ** *A *B *C ECN 236409 247589 261711 279731 Orig. of Change SFV SFV HMT HMT Submission Date See ECN See ECN See ECN See ECN Description of Change New silicon and new document - Preliminary Data Sheet. Changed the title to read "Final" data sheet. Updated Electrical Specifications chapter. Input all SFV memo changes. Updated Electrical Specifications chapter. Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add Solder Reflow Peak Temperature table. Clean up pinouts and fine tune wording and format throughout. Add new color and CY logo. Add URL to preferred dimensions for mounting MLF packages. Update Transmitter and Receiver AC Digital Block Electrical Specifications. Re-add ISSP pinout identifier. Delete Electrical Specification sentence re: devices running at greater than 12 MHz. Update Solder Reflow Peak Temperature table. Fix CY.com URLs. Update CY copyright. Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN E-Pad dimensions and rev. *A. Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs. Add OCD non-production pinout and package diagram. Update CY branding and QFN convention. Update package diagram revisions. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev. Tool section. Add CY8C20x34 to PSoC Device Characteristics table. Added Sawn pin information. Corrected Ordering Information to include CY8C24423A-24LTXI and CY8C24423A-24LTXIT Changed title to "CY8C24123A, CY8C24223A, CY8C24423A PSoC(R) Programmable System-on-ChipTM" Updated package diagram 001-30999 to *A. Added note on digital signaling in DC Analog Reference Specifications on page 27. Added Die Sales information note to Ordering Information on page 53. Updated Max package thickness for 32-pin QFN package Formatted Notes Updated "Getting Started" on page 4 Updated "Development Tools" on page 5 and "Designing with PSoC Designer" on page 6 *D 352614 HMT See ECN *E 424036 HMT See ECN *F *G *H *I 521439 HMT See ECN See ECN See ECN 2256806 UVS/PYRS 2425586 DSO/AESA 2619935 OGNE/AESA 12/11/2008 *J 2692871 DPT/PYRS 04/16/2009 Document Number: 38-12028 Rev. *J Page 54 of 55 [+] Feedback CY8C24123A CY8C24223A, CY8C24423A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-12028 Rev. *J Revised April 14, 2009 Page 55 of 55 PSoC DesignerTM and Programmable System-on-ChipTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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